May 19, 2018

Latching Cercuit (Controlling The motor by pressing Start Stop Button)

Latching Circuit for Motor Control – Ladder Logic Application

Objective:

Control a motor using a momentary Start and Stop push-button setup. Once the motor is turned ON using the Start button, it remains ON until the Stop button is pressed—even if the Start button is released.

Working Principle:

  • Start Button (I0.0): When pressed, it activates the motor.

  • Latching Logic: Keeps the motor energized using feedback from the output coil (Q0.0), forming a memory loop.

  • Stop Button (I0.1): Interrupts the circuit and stops the motor.

I/O Address Mapping

DeviceAddress
Start ButtonI0.0
Stop ButtonI0.1
Motor OutputQ0.0

Ladder Logic Program


 Explanation:

  • Rung 1 activates Q0.0 (Motor) when:

    • Start (I0.0) is pressed

    • AND Stop (I0.1) is NOT pressed

    • AND Motor output (Q0.0) is held ON through latching

  • The latching branch uses the motor’s output (Q0.0) to keep the rung true even after releasing the Start button.

  • Pressing the Stop button breaks the rung logic, de-energizing the motor.




 


AND & OR Gate Opertion in Ladder language

AND & OR Gate Operation Using Ladder Logic

🎯 Objective:

Control two lamps using four switches through:

  • AND Gate logic (series connection)
  • OR Gate logic (parallel connection)

📘 Application Description

We have four input switches and two output lamps. Two control scenarios are implemented:

Task 1 – AND Gate Logic (Series Connection)

  • Inputs: SW1 (I0.0), SW2 (I0.1)
  • Output: Lamp 1 (Q0.0)
  • Logic: Lamp 1 turns ON only if both SW1 and SW2 are turned ON.
  • Equivalent to: Q0.0 = I0.0 AND I0.1

Task 2 – OR Gate Logic (Parallel Connection)

  • Inputs: SW3 (I0.2), SW4 (I0.3)
  • Output: Lamp 2 (Q0.1)
  • Logic: Lamp 2 turns ON if either SW3 or SW4 is ON.
  • Equivalent to: Q0.1 = I0.2 OR I0.3

🧠 Input/Output Assignment

Device

Address

SW1

I0.0

SW2

I0.1

SW3

I0.2

SW4

I0.3

Lamp 1

Q0.0

Lamp 2

Q0.1

 

Network 1 :-The first rung connects SW1 and SW2 in series—mimicking an AND gate.

Network 2 :- The second rung connects SW3 and SW4 in parallel—mimicking an OR gate.